/******************************************************************************
*
* MODULE:    uart_TB.v
* DEVICE:     Test Bench
* PROJECT:   Tarea 2 Diseño Electronico Digital
* AUTHOR:    Ricardo Dávila Castro   
* DATE:      2010 19:35:08
*
* ABSTRACT:  Testbench receptor transmisor asincrono 
			con protocolo RS232 Ejercicio
*            
*******************************************************************************/
`timescale 1ns / 100ps

`ifndef 	UART_TB
`define    UART_TB

module uart_TB ;

reg clk_50M;
reg rxd;
reg aRST;

initial 
	begin
		clk_50M = 1'b1;
		forever #2 clk_50M = ~clk_50M;
	end
initial 
	begin
		aRST=1;
		#5 aRST = ~aRST;
		rxd = 0;
		#19201 rxd = 0;//inicio
		#19201 rxd = 1;//1
		#19201 rxd = 0;//2
		#19201 rxd = 1;//3
		#19201 rxd = 0;//4
		#19201 rxd = 1;//5
		#19201 rxd = 0;//6
		#19201 rxd = 1;//7
		#19201 rxd = 0;//8
		#19201 rxd = 1;//par
		#19201 rxd = 1;//stop
		#19201 rxd = 1;
		#19201 rxd = 1;
		#19201 rxd = 1;
		#99201 rxd = 0;
	end
uart uart_inst(.clk_50M(clk_50M),.aRST(aRST),.rxd(rxd));


endmodule
`endif